1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to techniques for testing integrated circuits.
2. Description of the Related Art
Integrated circuits, which may include microprocessors and other digital logic devices as well as analog and mixed-signal devices, may generally include a significant number of semiconductor components manufactured through complex fabrication processes. As manufacturing geometries shrink, complex designs including hundreds of millions of interconnected transistor devices become feasible. However, advances in integrated circuit density and design and manufacturing complexity significantly increase the challenge of ensuring that the resulting device is functional, reliable and capable of operating within expected performance and environmental parameters.
For example, as microprocessor implementations become increasingly sophisticated, it may become more difficult to functionally verify the design, as increased functional complexity may lead to a greater number of possibilities for error in implementation. Likewise, as device geometries shrink, opportunities for manufacturing defects increase due to manufacturing environment impurities, process inconsistency, and other factors.
Integrated circuits are often tested during the manufacturing process through the use of a test environment including sophisticated and expensive automated test equipment. Such test equipment typically interfaces with the integrated circuit using the electrical connections, commonly referred to as pins, provided by the integrated circuit's package. Owing to limitations on package sizes and increasingly complex integrated circuit input/output requirements, interface pins are often scarce resources, rendering it impractical to reserve large numbers of interface pins solely for dedicated testing purposes. Additionally, as integrated circuits become increasingly complex in design, it may become difficult to efficiently and reliably initiate integrated circuit testing without causing undesired operational side effects or increasing the burden of pre-manufacturing design verification.